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1 of 41 rev: 080206 note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, click here: www.maxim-ic.com/errata . general description the ds2790 provides a complete fuel gauging and protection solution for single cell li-ion battery packs. a low-power 16-bit maxq20 microcontroller with generous program and data memory, combined with an accurate measurement system for battery current, voltage, and temperature provide the ideal platform for customized fuelgauge algorithms. the 2-wire interface provides an i 2 c*- or smbus -compatible communication path between the host and battery pack, while providing password protected programming of the fuel-gauging firmware. eeprom data memory supports nonvolatile in-pack storage of charge parameters, cell characteristics, usage history, and manufacturing/lot tracking data. an autonomous state machine performs voltage, current, and temperature related protection functions. this capability increases reliability of the whole system by eliminating dependence on the cpu for protection. the ds2790 supports li-ion batteries in a wide range of applications. typical operating circuit ds2790 cc dc pls vin avss sda data pack+ pack- sns2 cp is2 is1 vdd 150 1k 100 100 1k 1k scl clk 150 [p0.0 - p0.5] 6 vss sns1 0.1 f 0.1 f 0.1 f r sns 2.5v (1) (1) 5.6v (1) 5.6v (1) optional for 8kv/15kv esd 1nf 2 pin configuration see last page for tssop and tdfn packages. features accurate current measurement for coulomb counting (current accumulation) 1.5% 4v over 64mv input range 1.5% 267a over 4.2a range using an external 15m series resistor high resolution current reporting 12-bit + sign average every 0.88ms 15-bit + sign average every 2.8s voltage measurement 10-bit average temperature measurement 10-bit using on-chip sensor 16-bit maxq20 low power microcontroller efficient c-language programming 8k words total program memory 4k words eeprom program memory 4k words rom program memory 64 words data eeprom 256 words data ram state machine-driven protection protection independent of cpu operation programmable levels for: overvoltage/undervoltage overcurrent temperature limits lithium-ion protector drives highside n-fets industry standard 400khz 2-wire interface password protected programming operates as low as 2.5v input on vdd sha-1 hash algorithm in rom internal oscillator no crystal required low power consumption 3.3ma cpu mode (1mhz), 280a analog mode, 4.5a sleep mode ordering information part temp range pin-package ds2790e+ -20oc to +70oc tssop-28 DS2790G+ -20oc to +70oc tdfn-28 contact factory concerning mask rom devices. + denotes lead-free package. maxq is a registered trademark of maxim integrated products, inc. smbus is a trademark of intel corp. * i 2 c is a philips corp. trademark. see acknowledgement at the end of the data sheet. ds2790 programmable 1-cell li-ion fuel gauge and protecto r www.maxim-ic.com
ds2790 programmable 1-cell li-ion fuel gauge and protector 2 of 41 absolute maximum ratings pls to v ss ............................................................................................................................... ................. -0.3v to +18v cp to v ss ............................................................................................................................... .................. -0.3v to +12v dc to v ss ............................................................................................................................... ............ -0.3v to cp+0.3v cc to v ss ............................................................................................................................... ..... v dd -0.3v to cp+0.3v p0.4, p0.5 to v ss ............................................................................................................................... -0.3v to v dd +0.3v avss to v ss ............................................................................................................................... ............. -0.3v to +0.3v all other pins to v ss ............................................................................................................................... ..... -0.3v to +6v scl, sda, p0.0?p0.5 continou s sink current ...................................................................... 20ma each, 50ma total p0.4, p0.5 continous s ource current .................................................................................... 20ma eac h, 50ma total cc, dc continuous source/sink current.......................................................................................... .....................5ma operating temperature range.................................................................................................... .......... -40oc to +85oc storage temperature range ...................................................................................................... ......... -55oc to +125oc soldering temperature ............................................................................. s ee ipc/jedec j-std-020a spec ification stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyone those indicated in the operational sections of t he specifications is not implied. exposure to the absolute maximum rating conditions for extended periods may affect device. dc electrical specifications (v dd = 2.5v to 5.5v, t a = -20 c to +70 c unless otherwise noted. typical values are at v dd = 3.7, t a = +25 c) parameter symbol conditions min typ max units i cpu cpu mode (note 1, 2) 1.5 3.3 ma i analog analog mode (note 2) 160 280 a sleep mode, (note 2) 12.0 sleep mode, (note 2) vdd = 4.2v, t a 50 c 2.5 4.5 supply current i sleep sleep mode, (note 2) v dd = 2.5v, t a 50 c 1.7 3.5 a brownout voltage v bo (note 3) 2.0 2.4 v power-on reset voltage v por (note 3) 1.5 v internal system clock f osci 1.0 mhz system clock error f err:osci 20 % osca active 1.0 system clock startup t su:osci from sleep, osca inactive 700 s pls voltage range (note 3) -0.3 15 v p0.4?p0.5 voltage range (note 3) -0.3 v dd + 0.3 v p0.0?p0.3, scl, sda voltage range (note 3) -0.3 +5.5 v scl, sda, input logic high v ih1 (note 3) 1.5 v scl, sda, input logic low v il1 (note 3) 0.6 v p0.0 - p0.5, input logic high v ih2 (note 3) 0.7 v dd v p0.0 - p0.5, input logic low v il2 (note 3) 0.3 v dd v scl, sda, p0.0?p0.5 output logic low: v ol1 i ol = 4ma, (note 3) 0.4 v p0.4?p0.5 output logic high: v oh1 i oh = -4ma, ppu[5:4] set, (note 3) v dd ? 0.5 v scl, sda pulldown current i pd1 v pin = v il1 , ppu[7:6] clear 0.3 1.2 3.0 a scl, sda pullup current i pu1 v pin = v ih1 , ppu[7:6] set 0.3 1.2 3.0 a p0.0?p0.3 pullup current i pu2 v pin = v ih2 , ppu[3:0] set 0.15 4 22 a
ds2790 programmable 1-cell li-ion fuel gauge and protector 3 of 41 parameter symbol conditions min typ max units p0.0?p0.5 pulse rejection t pr rising and falling edges 100 ns current measurement input range (full scale) v is1? v is2 -64 +64 mv current measurement resolution i lsb 15.625 v/r sns current measurement offset error i oerr -7.8 +7.8 v/r sns current measurement gain error i gerr -0.8 +0.8 % full scale oben = 1 -94 0 vh/day accumulated current offset q ca oben = 1, rsns = 0.015 -6.3 0 mah/day temperature measurement resolution t lsb 0.125 o c temperature measurement error t err -3 +3 o c voltage full scale v fs (note 4) 0 4.992 v voltage measurement resolution v lsb 4.88 mv voltage measurement error v err -20 +20 mv vin input resistance r in 15 m ? current measurement sample frequency f samp 1456 hz analog timebase frequency f osca 70 khz v dd 4.5v, t a = 25 o c -0.7 +0.7 analog timebase error f err:osca -2 +2 % filter resistors is1 to sns1, is2 to sns2 r ks 10 k ? eeprom copy time t eec v dd 2.8v 10 15 ms eeprom copy endurance data eeprom n eecd v dd 2.8v , t a = 50oc 50,000 cycles eeprom copy endurance program eeprom n eecp v dd 2.8v , t a = 50oc 1000 cycles electrical characteristics: protection circuitry (2.5v v dd 5.5v, t a = 0c to +50c.) parameter symbol conditions min typ max units output low: cc v olcc i ol = 0.1ma, (note 3) v dd + 0.1 v output low: dc v oldc i ol = 0.1ma, (note 3) 0.1 v output high: cc v ohcc i oh = -0.1ma, (note 3) v ocp - 0.25 v output high: dc v ohdc i oh = -0.1ma, (note 3) v ocp - 0.25 v output resistance: cc, dc r o v ocp = 9v, v pin = v ss 2.0 k ? output voltage: cp v ocp i cc + i dc 0.9 a, (note 3) 8.5 9.0 9.5 v overvoltage detect v ov ov = 01010b, (note 3) 4.330 4.350 4.370 v charge enable v ce ov = 01010b, (note 3) 4.230 4.250 4.270 v
ds2790 programmable 1-cell li-ion fuel gauge and protector 4 of 41 parameter symbol conditions min typ max units undervoltage detect v uv uvf = 10111b, (note 3) 2.430 2.450 2.470 v coct = doct = 00b 15.6 16 16.4 mv coct = doct = 01b 31.2 32 32.8 mv coct = doct = 10b 47.0 48 49.0 mv charge and discharge overcurrent detect (limits for charge thresholds are positive, while discharge is negative.) v oc coct = doct = 11b 62.7 64 65.3 mv doct = 00b 75 100 125 mv doct = 01b 105 140 175 mv doct = 10b 135 180 225 mv short-circuit detect v sc doct = 11b 165 220 275 mv overvoltage delay t ovd 0.8 1 1.2 s undervoltage delay t uvd 75 100 125 ms overcurrent delay t ocd 15 20 25 ms scdt = 1 1.5 2 2.5 ms short-circuit delay t scd scdt = 0 187 250 313 s secondary short-circuit delay t sscd (note 5) 20 200 s test threshold v tp 0.3 1.0 1.5 v test current i tst 10 20 40 a pulldown current, pls i pd sleep mode 200 a recovery charge current i rc vpls = 5.0v, v dd = 2.0v 0.5 1 2 ma electrical characteristics: 2-wire interface (2.5v v dd 5.5v, t a = -20 c to +70 c.) parameter symbol conditions min typ max units scl clock frequency f scl 0 400 khz bus free time between a stop and start condition t buf 1.3 s hold time (repeated) start condition t hd:sta (note 6) 0.6 s low period of scl clock t low 1.3 s high period of scl clock t high 0.6 s setup time for a repeated start condition t su:sta 0.6 s data hold time t hd:dat (note 7, 8) 0 0.9 s data setup time t su:dat (note 7) 100 ns rise time of both sda and scl signals t r (note 9) 20+0.1c b 300 ns fall time of both sda and scl signals t f (note 9) 20+0.1c b 300 ns
ds2790 programmable 1-cell li-ion fuel gauge and protector 5 of 41 parameter symbol conditions min typ max units setup time for stop condition t su:sto 0.6 s spike pulse width that can be suppressed by input filter t sp (note 10) 0 50 ns clock low time-out t timeout tto_dis = 0, (note 11) 25 35 ms cumulative clock low extend time for slave device t low:sext tls_dis = 0, (note 12) 25 ms cumulative clock low extend time for bus master t low:mext tto_dis = 0, tls_dis = 0 (note 13) 10 ms scl, sda input capacitance c bin 60 pf electrical characteristics: jtag interface (2.5v v dd 5.5v, t a = -20 c to +70 c.) parameter symbol conditions min typ max units jtag logic reference v ref v dd 2 v tck high time t th 4.0 s tck low time t tl 4.0 s tck low to tdo output t tlq 1.0 s tms, tdi input setup to tck high t dvth 1.0 s tms, tdi input hold after tck high t thdx 4.0 s note 1: maximum current assumuing 100% cpu duty cycle. note 2: this value does not include current in sda, scl, and p0.0?p0.5. note 3: all voltages referenced to v ss . note 4: voltage register can report up to 4.992v, however vin pin input saturation occurs at 4.75v minimum. note 5: the secondary short circuit delay is m easured from the falling transition on v dd to the resultant falling transition on dc. the delay is measured from the time v dd reaches v por - 0.5v to the time dc reaches 50% of v cp (4.5v). note 6: f scl must meet the minimum clock low time plus the rise/fall times. note 7: the maximum t hd:dat has only to be met if the device does not stretch the low period (t low ) of the scl signal. note 8: this device internally provides a hold time of at least 75ns for the sda signal (referred to the vihmin of the scl signal) to bridge the undefined region of the falling edge of scl. note 9: c b total capacitance of one bus line in pf. note 10: filters on sda and scl suppress noise spikes at the input buffers and delay the sampling instant. note 11: devices participating in data transfer will timeout when any clock low exceeds the minimum t timeout of 25ms. devices that have detected a timeout condition must reset the communication no later than the maximum t timeout of 35ms. the maximum value specified must be adhered to by both devices as it incorporates the cumulative stretch limit for the master (10ms) and slave device (25ms). note 12: t low:sext is the cumulative time the slave is allowed to extend the clock from the initial start to the stop. if the ds2790 exceeds this time, it will release both sda and scl and reset the communication interface. note 13: t low:mext is the cumulative time the master is allowed to extend the clock cycles within each byte of a communication sequence. if the bus master exceeds this time it is possible for the ds2790 to violate t timeout without having violated t low:sext .
ds2790 programmable 1-cell li-ion fuel gauge and protector 6 of 41 figure 1. 2-wire bus timing diagram sda scl t f t r t su;dat t low s t hd;sta t hd;dat t f t su;sta t hd;sta t su;sto t r t buf t sp sr p s figure 2. jtag timing diagram tck tdo tms / tdi v ref t th t tl t thd x t dvth t tlq
ds2790 programmable 1-cell li-ion fuel gauge and protector 7 of 41 pin description pin name description 1 n.c. no connection 2 n.c. no connection 3 cp charge pump output. bypass cp to v ss with 0.1 f. 4 pls pack plus. positive pack terminal connection. 5 dc discharge control. discharge fet gate drive output. 6 cc charge control. charge fet gate drive output. 7 scl 2-wire serial interface clock input and output 8 sda 2-wire serial interface data input and output 9 p0.0 programmable i/o pin. alternate functions: external interrupt input int0, [jtag tdi]. 10 p0.1 programmable i/o pin. alternate functions: external interrupt input int1, [jtag tms]. 11 sns2 current sense input. sns2 attaches to pack end of current sense resistor. 12 is2 current filter input 2 13 n.c. no connection 14 n.c. no connection 15 n.c. no connection 16 n.c. no connection 17 is1 current filter input 1 18 sns1 current sense input. sns1 attaches to battery end of current sense resistor and v ss . 19 avss analog supply return node. avss attaches to negative battery terminal. 20 v ss digital supply return node. v ss attaches to negative battery terminal. 21 p0.2 programmable i/o pin. alternate functions: reset input pin rst . 22 p0.3 programmable i/o pin. alternate functions: timer/counter input pin tck, [jtag tck]. 23 p0.4 programmable i/o pin. alternate function: [jtag tdo] 24 p0.5 programmable i/o pin 25 v dd input supply: +2.5v to +5.5v input range. bypass v dd to v ss with 0.1 f. 26 v in battery voltage sense input, measurement relative to avss. 27 n.c. no connection 28 n.c. no connection pad exposed pad (tdfn only). not electrically connected to ic. connect to v ss or leave floating.
ds2790 programmable 1-cell li-ion fuel gauge and protector 8 of 41 functional diagram maxq20 16-bit risc core jtag bootload and debug interface timer/ counter interrupt controller instruction oscillator (1mhz) precision analog oscillator 64 x 16 eeprom (data) 256 x 16 sram (data) 4k x 16 eeprom (program) 4k x 16 rom (utility) i 2 c interface and bootloader register file dp[0] dp[1] bp[offs] p0.3/tck p0.0/tdi p0.4/tdo p0.1/tms clk div fet charge pump vdd vdd_int cp current (is1 - is2) temperature voltage (vin - avss) a/d control vin vref ds2790 tci p0.3 ttck0:1 avg current analog front end adc / mux analog registers is1 is2 sns2 sns1 vss avss port pin drivers p0.0/int0/tdi p0.1/int1/tms p0.2/rst p0.3/tck p0.4/tdo p0.5 sda scl tx int0, int1 rx sci, sdi, sndi boi , vi, ci, ti watchdog timer wdi lithium ion protector sense & control pls fet drivers cc dc vss _int cci, bei sns1 sns2 vdd eeprom charge pump
ds2790 programmable 1-cell li-ion fuel gauge and protector 9 of 41 detailed description the following is an introduction to the primary features of the ds2790 programmable 1-cell li-ion fuel gauge and protector. more detailed descriptions of the device features can be found in the errata sheets, and user's guides described later in the additional documentation section. ds2790 overview the ds2790 incorporates the 16-bit maxq20 microcontroller core with 16 accumulators and 16-level hardware stack. four memory blocks provide application code space, utility code space, ram memory, and eeprom memory. specialized peripherals are integrated to perform battery monitoring, coulomb counting, lithium-ion protection, and 2-wire communication functions. the maxq20 core along with the specialized peripherals provide a flexible solution for fuel gauging and protection of lithium-ion battery packs. flexibility is further enhanced as the solution allows for upgrading of the program and data eeprom contents over the 2-wire interface. updates to the program and data eeprom are protected against unauthorized writes by a 256-bit user password. a read protection bit is provided to prevent reading either eeprom. maxq20 core architecture the ds2790 employs a maxq20 low-cost, high-performance, cmos, fully static, 16-bit risc microcontroller with eeprom memory. it is structured on a highly advanced, 16 accumulator-based, 16-bit risc architecture. fetch and execution operations are completed in one cycle without pipelining, since the instruction contains both the op code and data. the highly efficient core is supported by 16 accumulators and a 16-level hardware stack, enabling fast subroutine calling and task switching. data can be quickly and efficiently manipulated with three internal data pointers. multiple data pointers allow more than one function to access data memory without having to save and restore data pointers each time. the data pointers can automatically increment or decrement following an operation, eliminating the need for software intervention. instruction set the instruction set is composed of fixed-length, 16-bit instructions that operate on registers and memory locations. the instruction set is highly orthogonal, allowing arithmetic and logical operations to use any register along with the accumulator. special-function registers control the peripherals and are subdivided into register modules. the family architecture is modular, so that new devices and modules can reuse code developed for existing products the architecture is transport-triggered. this means that writes or reads from certain register locations can also cause side effects to occur. these side effects from the basis for higher-level op codes defined by the assembly, such as addc, or, jump, etc. the op codes are implemented as move instructions between certain register locations, while the assembler handles the encoding, which need not be a concern to the programmer. the 16-bit instruction word is designed for efficient execution. bit 15 indicates the format for the source field of the instruction. bits 0 to 7 of the instruction represent the source for the transfer. depending on the value of the format field, this can either be an immediate value or a source register. if this field represents a register, the lower four bits contain the module specifier and the upper four bits contain the register index in that module. bits 8 to 14 represent the destination for the transfer. this value always represents a destination register, with the lower four bits containing the module specifier and the upper three bits containing the register subindex within that module. any time that it is necessary to directly select one of the upper 24 registers as a destination, the prefix register pfx is needed to supply the extra destination bits. this prefix register write is inserted automatically by the assembler and requires only one additional execution cycle. see the maxq family user's guide for complete instruction set information.
ds2790 programmable 1-cell li-ion fuel gauge and protector 10 of 41 memory organization the ds2790 incorporates several memory areas: 4k words of utility rom contain a debugger, program loader, and sha-1 routines 4k words of eeprom memory for application program storage 256 words of sram for storage of temporary variables 64 words of eeprom memory for data storage 8 words of adc conversion data information 16-level stack memory for storage of program return addresses and general-purpose use the memory is implemented using the harvard architecture, with separate address spaces for program and data memory. a pseudo-von neumann memory map is also utilized placing rom, application code, and data memory into a single contiguous memory map. the pseudo-von neumann memory map allows data memory to be mapped into program space, permitting code execution from data memory. in addition program memory may be mapped into data space, permitting code constants to be accessed as data memory. figure 4 shows the ds2790?s memory map when executing from program memory space. see the maxq family user's guide: ds2790 supplement for memory map information when executing from data or rom space. the incorporation of eeprom memory allows field upgrade of the firmware. eeprom memory can be password protected with a 16-word key, denying access to program memory by unauthorized individuals. rom memory is also available for high-volume, low-cost applications. contact dallas semiconductor for more information on the availability of rom-based devices. figure 4. ds2790 memory map 16 16 stack ap system registers a pfx ip sp dpc dp 00h 0fh 8h 9h bh ch dh eh fh peripheral registers m0 m1 m2 00h 1fh 0h 1h 2h 4k 16 user program memory 0000h 0fffh 4k 16 utility rom 8000h 8fffh program memory space ffffh 256 16 sram data 0000h 00ffh 8 16 adc data 6003h 600ah data memory (word mode) ffffh 64 16 eeprom data 0100h 013fh 512 8 sram data 0000h 01ffh data memory (byte mode) ffffh 128 8 eeprom data 0200h 027fh 4k 16 utility rom 8000h 8fffh 4k 16 utility rom 8000h 9fffh
ds2790 programmable 1-cell li-ion fuel gauge and protector 11 of 41 stack memory a 16-bit, 16-level internal stack provides storage for program return addresses and general-purpose use. the stack is used automatically by the processor when the call, ret, and reti instructions are executed and interrupts serviced. the stack can also be used explicitly to store and retrieve data by using the push, pop, and popi instructions. on reset, the stack pointer, sp, initializes to the top of the stack (0fh). the call, push, and interrupt-vectoring operations increment sp, then store a value at the location pointed to by sp. the ret, reti, pop, and popi operations retrieve the value at ?@sp? and then decrement sp. utility rom the utility rom is a 4k word block of internal rom memory that defaults to a starting address of 8000h. the utility rom consists of subroutines that can be called from application software. these include: in-system programming (bootstrap loader) over jtag or 2-wire interfaces in-circuit debug routines internal self-test routines callable routines for in-application eeprom programming and sha-1 calculations following any reset, execution begins in the utility rom. the rom software determines whether the program execution should immediately jump to location 0000h, the start of application code, or to one of the special routines mentioned. routines within the utility rom are firmware-accessible and can be called as subroutines by the application software. more information on the utility rom contents is contained in the maxq family user's guide: ds2790 supplement . some applications require protection against unauthorized viewing of program code memory. for these applications, access to in-system programming, in-application programming, or in-circuit debugging functions is prohibited until a password has been supplied. the password is defined as the 16 words of physical program memory at addresses x0010h to x001fh. upon startup, code in the rom examines the password, if a password is defined (password is other than all zero?s or all one?s), the pwl bit remains set, which prohibits access to commands to read memory contents over the jtag and 2-wire interfaces. a single password lock (pwl) bit is implemented in the sc register. when the pwl is set to one (power-on reset default), the password is required to access the utility rom, including in-circuit debug and in-system programming routines that allow reading or writing of internal memory. when pwl is cleared to zero, these utilities are fully accessible without password. the password is automatically set to all ones following a mass erase. programming the eeprom memory of the microcontroller can be programmed by two different methods: in-system programming and in-application programming. both methods afford great flexibility in system design as well as reduce the life-cycle cost of the embedded system. these features can be password protected to prevent unauthorized access to code memory. in-system programming an internal bootstrap loader allows the device to be programmed over the jtag or 2-wire interfaces. as a result, system software can be upgraded in-system, eliminating the need for a costly hardware retrofit when software updates are required. remote software uploads are possible that enable physically inaccessible applications to be frequently updated. the jtag interface hardware can be a jtag connection to another microcontroller, or a connection to a pc serial port using a serial to jtag converter such as the maxqjtag-001, available from maxim integrated products. the 2-wire interface hardware can be an i 2 c connection to another microcontroller, or a connection to a pc usb port using a usb to i 2 c converter such as the ds9123o, available from dallas semiconductor. a commercial gang programmer can also be used for programming.
ds2790 programmable 1-cell li-ion fuel gauge and protector 12 of 41 activating the jtag interface and loading the test access port (tap) with the system programming instruction invokes the bootstrap loader for use over the jtag interface. setting the spe bit to 1 during reset through the jtag interface executes the bootstrap-loader-mode program that resides in the utility rom. when programming is complete, the bootstrap loader can clear the spe bit and reset the device, allowing the device to bypass the utility rom and begin execution of the application software. performing a program request over the 2-wire interface also invokes the bootstrap loader. the user must successfully complete a password match (if pwl = 1). the bootstrap loader functions are then fully supported over the 2-wire interface. when programming is complete, the exit loader function is used to reset the ds2790 and begin execution of the application software. the following bootstrap loader functions are supported: information commands load eeprom code and data dump eeprom code and data crc eeprom code and data verify eeprom code and data erase eeprom code and data in-application programming the in-application programming feature allows the microcontroller to modify its own eeprom program memory. this allows on-the-fly software updates in mission-critical applications that cannot afford downtime. alternatively, it allows the application to develop custom loader software that can operate under the control of the application software. the utility rom contains firmware-accessible eeprom programming functions that erase and program eeprom memory. these functions are described in detail in the maxq family user's guide: ds2790 supplement . system timing the ds2790 generates its 1mhz instruction clock (osci) internally. this quick starting oscillator is used for instruction fetch and execution by the maxq20 core.. the analog oscillator (osca) is a band-gap based rc oscillator that is trimmed to better than 2% accuracy. the analog clock runs independent of osci and serves as the clock source for the adc, watchdog timer, interval timer, and 2-wire timeouts. osci is enabled through either a system interrupt or system por and disabled through a system stop. a voltage brown out detection circuit disables osci if vdd falls below v bo . once vdd raises above v bo , a hysteresis circuit waits t su:osci before re-enabling osci. osca is enabled by the watchdog timer signals ewdi or ewt, the timer / counter (tmod), or by the protection circuitry (pmm[1:0]). figure 5. system clocks interrupt stop pmm.0 pmm.1 ewdi tmod 1mhz oscillator br own out hyster esis (t su :osc i ) 70khz oscillator brown out detector osci enable osca enable en en en clk dq clr por osca osci vdd < v bo ewt
ds2790 programmable 1-cell li-ion fuel gauge and protector 13 of 41 system reset several reset sources are provided for microcontroller control. although code execution is halted in the reset state, osci continues to run. power-on reset - an internal power-on reset circuit enhances system reliability. this circuit forces the device to perform a power-on reset whenever a rising voltage on v dd climbs above v por . at this point the following events occur: all registers and circuits enter their reset state, the por flag (wdcn.7) is set to indicate the source of the reset, code execution begins at location 8000h watchdog timer reset - a few differences exist between the watchdog timer in the ds2790 and the one described in the maxq family user's guide as described in the watchdog timer section. software can determine if a reset is caused by a watchdog timeout by checking the watchdog timer reset flag (wtrf) in the wdcn register. execution resumes at location 8000h following a watchdog timer reset. external system reset - asserting the external rst (port p0.2) pin low causes the device to enter the reset state. the external reset function is described in the maxq family user's guide . execution resumes at location 8000h after the rst pin is released. maxq20 core power management the ds2790 is designed for low power battery monitoring applications. the peripherals have been designed with the ability to wake the processor from stop mode any time software intervention is needed. power management is optimized in the applications by performing any necessary processing as quickly as possible, and re-entering the low power stop mode. processing resumes from stop mode via any of the following sources (when enabled): an external interrupt is triggered. an external reset signal is applied to the rst pin. a watchdog timer interrupt occurs. an internal interrupt event occurs. no division of the internal system clock is supported, subsequently the pmme and cd[1:0] bits described in the maxq users guide are not implemented in the ds2790. watchdog timer the watchdog timer provides a mechanism to reset the processor in the case of undesirable code execution. the watchdog timer is a hardware timer designed to be periodically reset by the application software. if the software operates correctly, the timer is reset before it reaches its maximum count. however, if undesireable code execution prevents a reset of the watchdog timer, the timer reaches its maximum count and resets the processor. the watchdog timer in the ds2790 differs in two respects from the one described in the maxq family user's guide : 1) the clock used by the timer is the 70khz osca clock that runs independently of the 1mhz osci (or system) clock, and 2) the watchdog interrupt is an asynchronous interrupt that can bring the processor out of stop mode. the watchdog timer is controlled through bits in the wdcn register. its timeout period can be set to one of the four programmable intervals ranging from 2 12 to 2 21 osca clock periods ( 59ms up to 30s ). the watchdog interrupt occurs at the end of this timeout period, which is 512 osca clock periods, or 7.3ms, before the reset.
ds2790 programmable 1-cell li-ion fuel gauge and protector 14 of 41 ds2790 power modes when power is first applied to the ds2790, a power-on-reset (por) circuit transitions the ic to brown-out state where cell voltage is monitored. if v dd voltage is above the brown-out threshold v bo , the ds2790 enters cpu state and begins code execution. firmware determines if the ic switches to analog state or low-power sleep states when a stop halts cpu operation. the ds2790 enters sleep state after a cpu stop if the adc, the protector, and all internal timers are disabled. in sleep state, all ic operation becomes inactive except for external activity interrupts. brown-out detection does not occur in sleep state. any interrupt generated by 2-wire port communication, external input on ports p0.0 or p0.1, or a charger detection on pls will transition the ds2790 from sleep to brown-out to verify cell voltage before returning to cpu state. the ds2790 enters analog state after a cpu stop if any one of the following is active: the adc, the protector, the interval timer or the watchdog timer. an external interrupt or an interrupt from any active internal circuit causes the ds2790 to transition back to cpu state to service the condition. if the ds2790 is in analog or cpu state, and vdd falls below v bo , a brown-out condition occurs and the ds2790 enters the brown-out state. in brown-out state, the processor is halted without changing the instruction pointer. if v dd voltage rises above v bo within a time of t su:osci , the ds2790 returns to cpu state and generates a brown-out interrupt (if enabled). otherwise, if v dd remains below v bo for t su:osci , the ds2790 enters an inactive state where it waits for a charger to be applied. when charge voltage is sensed on pls, the ds2790 returns to the brown-out state where v dd voltage is verified before returning to cpu state. figure 3. ds2790 state diagram cpu mode code execution brown-out cpu and protector disabled . analog mode adc & protector active sleep mode external interrupts monitored ic inactive charger detect v pls > v in + 0.15v brown-out timeout t > t su:osci brown-out vdd < v bo external interrupt cpu stop analog circuits inactive brown-out recovery vdd > v bo for t su:osci brown-out vdd < v bo interrupt cpu stop analog circuits active por
ds2790 programmable 1-cell li-ion fuel gauge and protector 15 of 41 register set most functions of the device are controlled by sets of registers. these registers provide a working space for memory operations as well as configuring and addressing peripheral registers on the device. registers are divided into two major types: system registers and peripheral registers. the common register set, also known as the system registers, includes the alu, accumulator registers, data pointers, interrupt vectors and control, and stack pointer. the peripheral registers define additional functionality that may be included by different products based on the maxq20 architecture. this functionality is broken up into discrete modules so that only the features required for a given product need to be included. table 1 shows the ds2790 register set. table 1. system register map module name (base specifier) register index ap (8h) a (9h) pfx (bh) ip (ch) sp (dh) dpc (eh) dp (fh) 00h ap a[0] pfx ip ? ? ? 01h apc a[1] ? ? sp ? ? 02h ? a[2] ? ? iv ? ? 03h ? a[3] ? ? ? offs dp0 04h psf a[4] ? ? ? dpc ? 05h ic a[5] ? ? ? gr ? 06h imr a[6] ? ? lc0 grl ? 07h ? a[7] ? ? lc1 bp dp1 08h sc a[8] ? ? ? grs ? 09h ? a[9] ? ? ? grh ? 0ah ? a[10] ? ? ? grxl ? 0bh iir a[11] ? ? ? fp ? 0ch ? a[12] ? ? ? ? ? 0dh ? a[13] ? ? ? ? ? 0eh ckcn a[14] ? ? ? ? ? 0fh wdcn a[15] ? ? ? ? ? note: names that appear in italics indicate that all bits of a register are read-only. names that appear in bold indicate that a regi ster is 16 bits wide. registers in module ap are bit addressable.
ds2790 programmable 1-cell li-ion fuel gauge and protector 16 of 41 table 2. system register bit functions register bit number register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ap ? ? ? ? ap (4 bits) apc clr ids ? ? ? mod2 mod1 mod0 psf z s ? gpf1 gpf0 ov c e ic ? ? cgds ? ? ? ins ige imr ims ? ? ? ? ? im1 im0 sc tap ? ? ? ? rod pwl ? iir iis ? ? ? ? ? ii1 ii0 ckcn ? ? ? ? ? ? ? ? wdcn por ewdi ? ? wdif wtrf ewt rwt a[n] (0..15) a[n] (16 bits) pfx pfx (16 bits) ip ip (16 bits) sp ? ? ? ? ? ? ? ? ? ? ? ? sp (4 bits) iv iv (16 bits) lc[0] lc[0] (16 bits) lc[1] lc[1] (16 bits) offs offs (8 bits) dpc ? ? ? ? ? ? ? ? ? ? ? wbs2 wbs1 wbs0 sdps1sdps0 gr gr.15 gr.14 gr.13 gr.12 gr.11 gr.10 gr.9 gr .8 gr.7 gr.6 gr.5 gr.4 gr.3 gr.2 gr.1 gr.0 grl grl.7 grl.6 grl.5 grl.4 grl.3 grl.2 grl.1 grl.0 bp bp (16 bits) grs grs.15 grs.14 grs.13 grs.12 grs.11 grs.10 grs.9 g rs.8 grs.7 grs.6 grs.5 grs.4 grs.3 grs.2 grs.1 grs.0 grh grh.7 grh.6 grh.5 grh.4 grh.3 grh.2 grh.1 grh.0 grxl grxl.15 grxl.14 grxl.13 grxl .12 grxl.11 grxl.10 grxl.9 grxl.8 grxl.7 grxl.6 grxl.5 grxl.4 grxl.3 grxl.2 grxl.1 grxl.0 fp fp (16 bits) dp[0] dp[0] (16 bits) dp[1] dp[1] (16 bits)
ds2790 programmable 1-cell li-ion fuel gauge and protector 17 of 41 table 3. system register bit reset values register bit register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ap 0 0 0 0 0 0 0 0 apc 0 0 0 0 0 0 0 0 psf 1 0 0 0 0 0 0 0 ic 0 0 0 0 0 0 0 0 imr 0 0 0 0 0 0 0 0 sc 0 0 0 0 0 0 s 0 iir 0 0 0 0 0 0 0 0 ckcn 0 s s 0 0 0 0 0 wdcn s s 0 0 0 0 0 0 a[n] (0..15) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pfx 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ip 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sp 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 iv 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 lc[0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 lc[1] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 offs 0 0 0 0 0 0 0 0 dpc 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 gr 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 grl 0 0 0 0 0 0 0 0 bp 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 grs 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 grh 0 0 0 0 0 0 0 0 grxl 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 fp 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dp0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dp1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 note: s indicates bit reflects pin state
ds2790 programmable 1-cell li-ion fuel gauge and protector 18 of 41 table 4. peripheral register map module module register index m0 (0h) m1 (1h) m2 (2h) register index m0 (0h) m1 (1h) m2 (2h) 00h po twsint ? 10h ? ? ? 01h ppu twsim ? 11h ? ? ? 02h paf twscmd ? 12h ? ? ? 03h eic twscfg ? 13h ? ? ? 04h eint twstxd/rxd ? 14h ? ? ? 05h prot ? ? 15h ? ? ? 06h tc ? ? 16h ? ? ? 07h tcc ? ? 17h ? ? ? 08h pi ? ? 18h icdt0 ? ? 09h ? twsfif ? 19h icdt1 ? ? 0ah ? ? ? 1ah icdc ? ? 0bh ? ? ? 1bh icdf ? ? 0ch ? ? ? 1ch icdb ? ? 0dh ? ? ecntl 1dh icda ? ? 0eh ? ? eaddr 1eh icdd ? ? 0fh ? ? edata 1fh ? ? ? note: names that appear in italics indicate that all bits of a register are read-only. names that appear in bold indicate that a regi ster is 16 bits. all locations are bit addressable.
ds2790 programmable 1-cell li-ion fuel gauge and protector 19 of 41 table 5. peripheral register bit functions register bit number register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 po ? ? po.5 po.4 po.3 po.2 po.1 po.0 ppu sda_pu scl_pu ppu.5 ppu.4 ppu.3 ppu.2 ppu.1 ppu.0 paf ? rstd paf.5 paf.4 paf.3 paf.2 paf.1 paf.0 eic mboi msci msdi msndi mcci mbei mvi mci mti mtci pip.1 pip.0 pit.1 pit.0 pie.1 pie.0 eint boi sci sdi sndi cci bei vi ci ti tci ? ? ? rst int.1 int.0 prot cocf docf scf ovf uvf ? cc dc ? ? ? ? ce de pmm.1 pmm.0 tc thi.7 thi.6 thi.5 thi.4 thi.3 thi.2 thi.1 thi.0 tlow.7 tlow.6 tlow.5 tlow.4 tlow.3 tlow.2 tlow.1 tlow.0 ttc ? ? ? ? ? ttck.1 ttck.0 tmod pi sda scl pi.5 pi.4 pi.3 pi.2 pi.1 pi.0 icdt0 icdt0.15 icdt0.14 icdt0.13 icdt0.12 icdt0.11 icdt0.10 icdt0.9 icdt0.8 icdt0.7 icdt0.6 icdt0.5 icdt0.4 icdt0.3 icdt0.2 icdt0.1 ic dt0.0 icdt1 icdt1.15 icdt1.14 icdt1.13 icdt1.12 icdt1.11 icdt1.10 icdt1.9 icdt1.8 icdt1.7 icdt1.6 icdt1.5 icdt1.4 icdt1.3 icdt1.2 icdt1.1 ic dt1.0 icdc dme ? rege ? cmd.3 cmd.2 cmd.1 cmd.0 icdf ? ? ? ? pss.1 pss.0 spe txc icdb icdb.7 icdb.6 icdb.5 icdb.4 icdb.3 icdb.2 icdb.1 icdb.0 icda icda.15 icda.14 icda.13 icda.12 icda.11 icda.10 icda.9 icda.8 icda.7 icda.6 icda.5 icda.4 icda.3 icda.2 icda.1 icda.0 icdd icdd.15 icdd.14 icdd.13 icdd.12 icdd.11 icdd.10 icdd.9 icdd.8 icdd.7 icdd.6 icdd.5 icdd.4 icdd.3 icdd.2 icdd.1 icdd.0 twsint ? ? ? ? timeout stop restart _read restart _write start txd_ byte txd_ empty txd_ full rxd_ cmd rxd_ byte rxd_ empty rxd_ full twsim ? ? ? ? timeout_ mask stop_ mask restart _read _mask restart _write _mask start_ mask txd_ byte_ mask txd_ empty_ mask txd_ full_ mask rxd_ cmd_ mask rxd_ byte_ mask rxd_ empty_ mask rxd_ full_ mask twscmd twscmd .7 twscmd .6 twscmd .5 twscmd .4 twscmd .3 twscmd .2 twscmd .1 twscmd .0 twscfg addr.6 addr.5 addr.4 addr.3 addr.2 addr.1 addr.0 0 0 0 0 tout_ long tls_dis tto_dis cmd_hm cmd_hm_ dis twstxd/rxd txd/rxd .7 txd/rxd .6 txd/rxd .5 txd/rxd .4 txd/rxd .3 txd/rxd .2 txd/rxd .1 txd/rxd .0 twsfif ltx.3 ltx.2 ltx.1 ltx.0 lrx.3 lrx.2 lrx.1 lrx.0 note: names that appear in italics indicate a read-only register bit.
ds2790 programmable 1-cell li-ion fuel gauge and protector 20 of 41 table 6. peripheral register reset values register bit number register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 po 0 0 1 1 1 1 1 1 ppu 0 0 0 0 0 1 0 0 paf 0 0 0 0 0 1 0 0 eic 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 eint 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 prot 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ttc 0 0 0 0 0 0 0 0 pi s s s s s s s s icdt0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 icdt1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 icdc 0 0 0 0 0 0 0 0 icdf 0 0 0 0 0 0 0 0 icdb 0 0 0 0 0 0 0 0 icda 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 icdd 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 twsint 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 twsim 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 twscmd 0 0 0 0 0 0 0 0 twscfg 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 twstxd/rxd 0 0 0 0 0 0 0 0 twsfif 0 0 0 0 0 0 0 0 note: s indicates bit reflects pin state.
ds2790 programmable 1-cell li-ion fuel gauge and protector 21 of 41 system interrupts multiple interrupt sources are available for quick response to internal and external events. the maxq20 architecture uses a single interrupt vector (iv), single interrupt-service routine (isr) design. for maximum flexibility, interrupts can be enabled globally, individually, or by module. when an interrupt condition occurs, its individual flag is set, even if the interrupt source is disabled at the local, module, or global level. interrupt flags must be cleared within the firmware-interrupt routine to avoid repeated interrupts from the same source. application software must ensure a delay between the write to the flag and the reti instruction to allow time for the interrupt hardware to remove the internal interrupt condition. asynchronous interrupt flags require a one-instruction delay and synchronous interrupt flags require a two-instruction delay. when an enabled interrupt is detected, execution jumps to a user-programmable interrupt vector location. the iv register defaults to 0000h on reset or power-up, so if it is not changed to a different address, application firmware must determine whether a jump to 0000h came from a reset or interrupt source. once control has been transferred to the isr, the interrupt identification register (iir) can be used to determine if a system register or peripheral register was the source of the interrupt. the specified module can then be interrogated for the specific interrupt source and software can take appropriate action. interrupts are evaluated by application code allowing the definition of a unique interrupt priority scheme for each application. interrupt sources are available from the watchdog timer described in the maxq users guide , the twsint register described in the 2-wire interface section, and the eint register as shown in figure 6. eint register the eint register contains interrupts generated by the adc, the timer-counter, the protection circuits, the general purpose port pins and the serial-interface port pins. their masks and their configuration bits, along with the rst pin status and control, are present in the eic and paf registers of module 0.
ds2790 programmable 1-cell li-ion fuel gauge and protector 22 of 41 figure 6. eint register interrupt sources generator interrupt mask description frequency int0 paf.0/pie.0 the interrupt from pin p0.0 is configurable via the paf.0, pit.0 and pip.0 bits. dependent on external conditions. int1 paf.1/pie.1 the interrupt from pin p0.1 is configurable via the paf.1, pit.1 and pip.1 bits. dependent on external conditions. sci msci the serial connect interrupt is generated when all serial lines become high. every time all lines are high after any of them were low. sdi msdi the serial disconnect interrupt is generated when all serial lines are low for at least 220ms. once every 220ms if all serial lines are held low. the first interrupt may take up to 440ms from the time all lines go low. interrupt will not trigger if the adc is off. sndi msndi the serial not disconnected interrupt is generated when only one serial line goes high. every time any line goes high after all of them were low. ports and pins cci mcci the charger connection interrupt is generated when v pls increases above v in and creates a charger detection condition. each time the charger detection condition evaluates to true after it was false. brown-out detector boi mboi the brown-out interrupt indicates that v dd was below v bo in the past. it will not terminate the microcontroller's stop mode. it will interrupt the microcontroller, if mboi is 1, after a charger brings v dd above v bo and causes the microcontroller to run. every time after exiting brown-out. protection logic bei mbei the battery event interrupt is an interrupt for a collection of events that initiate the various battery conditions that are handled by the protection logic: overvoltage, undervoltage, charge overcurrent, discharge overcurrent and short-circuit. the battery conditions are available as flags in the mas register of module 0. each entry into a protection violation. vi mvi the voltage interrupt indicates the voltage register in the data peripheral memory block has a fresh voltage average. once every 6.9ms. never if the adc is off. ci mci the current interrupt indicates that the quick average current register in the data peripheral memory block has a fresh reading and that the acr has also been updated. once every 88ms. never if the adc is off. a/d converter ti mti the temperature interrupt indicates that the temperature register in the data peripheral memory block has a fresh average. once every 220ms. never if the adc is off. timer/ counter tci mtci the timer/counter interrupt indicates that the timer/counter has been reloaded after reaching its end-count. dependent on tmod and ttck[1:0].
ds2790 programmable 1-cell li-ion fuel gauge and protector 23 of 41 i/o ports the ds2790 includes a simple input/output (i/o) data port. from a software perspective, the port appears as a group of special function registers within module m0. the simple i/o port defined for this product is described below: cmos input buffers four open drain output drivers with selectable tri-state or weak pullups two selectable open drain or push-pull output drivers with selectable tri-state support alternate functions and tap controller interface signals two pins have interrupt capability the port is accessed through five peripheral registers (po, pi, paf, ppu, and eic) addressed either by byte or by individual bit locations. the i/o port is designed to provide programming flexibility for the application. all individual i/o pins are independently configured; and can be defined as an input, output, or alternate function. table 7 summarizes the functionality of the i/o pins. table 7. i/o port pins functions characteristics primary alternate tap * bidirectional weak passive pulldown weak active pullup strong active pullup p0.0 int0 tdi * configurable, [in] - configurable, [off] - p0.1 int1 tms * configurable, [in] - configurable, [off] - p0.2 rst* configurable, [in] - configurable, [off] - p0.3 - tck * configurable, [in] - configurable, [off] - p0.4 - tdo* configurable, [in] - - configurable, [off] p0.5 - - configurable, [in] - - configurable, [off] sda - - yes configurable, [on] configurable, [off] - scl - - yes configurable, [on] configurable, [off] - note: reset values are denoted with an * and by []. pi register : the pi register is a read only input of the i/o pins. when the register is read, the logic level of each pin is reported in the corresponding bit locations. reading a logic low or high on a pin does not change the output drive on that pin. po register : the po register controls the output state of the i/o pins. data written to this register determines the pin output drive. when a bit is written to a ?0? (cleared), the n-channel output drive transistor is enabled, and the pullup is disabled. when bit is written to a ?1? (set), the n-channel output drive transistor is disabled, and the pullup enabled (if so configured). the po bits are set asynchronously during power-on reset to disable the n-channel output drive. po bits are not altered in sleep mode, however drive to the n-channel is disabled. ppu register : the ppu register contains independent bits that define each pin as hi-z or pulled up when its n- channel output drive transistor is disabled. p0.0 through p0.3 have weak pullups, p0.4 and p0.5 have strong pullups. when the output is disabled and the ppu bit is cleared, the pin is high impedance. when the output is disabled and the ppu bit is set, the pin?s weak or strong pullup is enabled. when the ppu bit is set and the device enters stop mode, the weak pullup remains enabled. paf register : the paf register enables or disables the alternat e functions of p0.0-p0.2. when a pin?s paf bit is cleared, the pin is controlled by the pi, po, ppu, and eic registers. when the paf bit is set, the pin operates in it?s alternate function mode. the rst function of p0.2 can be disabled by writing the rstd bit to 1. eic register : the lower six bits of the eic register are the port interrupt control bits. the port interrupt control bits are used to enable and configure detection of external interrupts. interrupt enable bits, pie.0 and pie.1, enable detection of an interrupt on pins p0.0 and p0.1 respectively. interrupt type bits, pit.0 and pit.1, define the type (level or edge) of interrupt on pins p0.0 and p0.1 respectively. interrupt polarity bits, pip.0 and pip.1, determine the interrupt polarity on pins p0.0 and p0.1, respectively.
ds2790 programmable 1-cell li-ion fuel gauge and protector 24 of 41 table 8. p0 interrupt configuration pie.x pit.x pip.x result 0 x x interrupt disabled 1 0 0 interrupt enabled, triggered on logic low 1 0 1 interrupt enabled, triggered on logic high 1 1 0 interrupt enabled, triggered on falling edge 1 1 1 interrupt enabled, triggered on rising edge figure 7. port pin schematics pi.x ppu.x p0.x interrupt detect pie.x pip.x pit.x paf.x int.x po.x stop pmm.0 pmm.1 ports p0.0 and p0.1 pi.2 ppu.2 p0.2 reset paf.2 rstd po.2 stop port p0.2 pi.x ppu.x p0.x po.x stop ports p0.3-p0.5 p0.3 p0.4, p0.5 sda/scl in sda/ scl sda/scl pull-up sda/scl out scl and sda pmm.0 pmm.1 pmm.0 pmm.1
ds2790 programmable 1-cell li-ion fuel gauge and protector 25 of 41 programmable timer/counter the timer/counter block operates as a simple 8-bit interval timer or counter. the start value is programmable and is automatically reloaded when a rollover occurs. the tmod bit in the tcc register selects between the counter and timer modes. in the counter mode, external events on the p0.3 pin are counted. in the timer mode, osca clock source cycles are counted. the osca clock and brown-out detectors continue to run if the cpu is stopped. figure 8. timer / counter block diagram 07 tlow 07 thi osca 14.3us 343us 6.86ms 220ms 2 tci interrupt ttck[1:0] reload p0.3 0 1 tmod the timer low byte (tlow) is used to count input events, while the timer high byte (thi) is used to store the reload value. firmware must initialize tlow and thi with the same value for the first count to be the same as succeeding counts. tlow counts up until ffh is reached, it is then automatically reloaded with the value in thi. thi remains unchanged unless modified by firmware. the clock source is selected with ttck[1:0] bits. the following table describes the possible resolution and range of the timer. table 9. programmable timer configuration tmod ttck[1:0] clock period timer range ( t * 2 8 ) 1 0 0 14.3s 3.66ms 1 0 1 343s 87.9ms 1 1 0 6.86ms 1.76s 1 1 1 220ms 56.3s 0 n/a counter mode 2-wire slave peripheral interface module a 2-wire serial-peripheral interface for interconnection with external devices is incorporated into the ds2790. the 2-wire slave (tws) peripheral allows interrupt driven i 2 c or smbus device communication with a minimal amount of cpu overhead. a transmit/recieve data register (twstxd/rxd) handles byte level data transfers and the tws fifo register (twsfif) monitors the usage of the transmit and receive buffers. the 2-wire slave command register (twscmd) maintains the command byte of every communication sequence for use by the maxq20 core. configuration of the 2-wire interface is handled through the tws configuration register (twscfg) allowing system software to change the ds2790?s slave address, control handshaking on the clock line, and control bus timeout settings. the asynchronous interface between the tws and maxq20 core is handled by tws generated interrupts reported in the interrupt register (twsint) and controlled in interrupt mask register (twsim).
ds2790 programmable 1-cell li-ion fuel gauge and protector 26 of 41 figure 9. 2-wire slave confi guration register (twscfg) field bit format allowable values addr 15:9 r/w 2-wire slave address. default = 0001011b reserved 8:5 r reserved bits read as 0000b tout_long 4 r/w lengthen timeouts. only valid if t timeout or t low:sext timout is enabled. 0 = t low:sext ? nominal 15ms t timeout ? nominal 30ms 1 = t low:sext ? nominal 60ms t timeout ? nominal 120ms tls_dis 3 r/w t low:sext disable 0 = t low:sext timeout is enabled 1 = t low:sext timeout is disabled tto_dis 2 r/w t timeout disable 0 = t timeout is enabled 1 = t timeout is disabled cmd_hm 1 r/w only valid if cmd_hs_dis = 0. 0 = (ce) clock extend until command register release latch is cleared or clock extend timeout. 1 = (nack) nack the command byte if command register release latch is clear. cmd_hm_dis 0 r/w command handshake mode disable. 0 = command handshake mode is enabled. 1 = command unconditionally accepted. note: the peripheral handles clock extension and ack/nack generation without intervention from the maxq20 core. bus timeout conditio ns detailed in the 2-wire specification, t timeout and t low:sext , are also handled directly by the tws hardware. command register and handshaking during a write, the first byte after the slave address is the command byte. the command byte signifies how the data following the command byte should be interpreted. it is useful for software to have access to this command byte during the entire 2-wire transaction. therefore, the command byte is stored in the command register (twscmd) and handshaking between the 2-wire master and cpu is implemented to ensure that the comm and byte has been processed by the cpu before a new command byte can be received. handshaking is configured in the 2-wire configuration register (twscfg); and the following handshaking modes can be implemented: cmd_hm_dis=1, cmd_hm=x handshaking disabled. all new command bytes are unconditionally written to the twscmd register and acknowledged (ack) by the 2-wire hardware. cmd_hm_dis=0, cmd_hm=0 upon receipt of a new command byte, the twscmd register becomes ?busy?. the twscmd register will remain busy and can not accept a new command byte until the cpu executes a ?dummy? write to the twscmd register. the dummy write clears the busy state of the twscmd register so that it can accept a new command byte. if the master attempts to send additional command bytes while the twscmd register is busy, the 2-wire hardware will begin clock extending; which will continue until the cpu executes a dummy write to the twscmd register or the smbus timeout limits are reached (if enabled). cmd_hm_dis=0, cmd_hm=1 in this mode, if the master attempts to send additional command bytes while the twscmd register is busy, the 2-wire hardware will not acknowledge (nack) the command byte. the master can re-attempt to send the command byte until it is ack?ed.
ds2790 programmable 1-cell li-ion fuel gauge and protector 27 of 41 2-wire slave interrupts an interrupt is generated when any condition that sets an interrupt status register bit occurs, and the corresponding interrupt mask bit in the 2-wire slave interrupt mask register (twsim) is also set. all 2-wire interrupts are maskable by clearing the corresponding bit in the twsim. upon system reset, all 2-wire interrupt mask bits are cleared automatically. the interrupt status register is 2 bytes in length and is readable and writeable by the maxq20 core. like the high level interrupt status register in the core, when the twsint register is read, the state of the interrupt status bits are returned but not altered. edge triggered interrupt status bits are cleared by writing a ?0? to their location. any attempt to write a ?1? is ignored. level triggered interrupt status bits are cleared automatically after the event that caused the interrupt to occur has ended. table 10. 2-wire slave interrupt sources interrupt (twsint) mask (twsim) description trigger rxd_full rxd_full_mask when the rxd fifo is full. level rxd_empty rxd_empty _mask rxd buffer is empty. edge rxd_byte rxd_byte_mask byte moved from the incoming shift register to the rxd fifo. edge rxd_cmd rxd_cmd_mask command byte receive completed. edge txd_full txd_full_mask txd buffer is full. edge txd_empty txd_empty _mask when the txd fifo is empty. level txd_byte txd_byte_mask byte moved from txd fifo to the outgoing shift register. edge start start_mask a start followed by the address defined in the configuration register was recognized. (this bit is not set during a repeated start condition.) edge restart _write restart_write _mask a repeated start followed by the address defined in the configuration register was received with the read/write bit clear. edge restart _read restart_read _mask a repeated start followed by the address defined in the configuration register was received with the read/write bit set. edge stop stop_mask after an address qualified start or restart, a stop is recognized on the bus. edge timeout timeout_mask t timeout or t low:sext event recognized on the bus. either timeout event will reset the tws interface. edge transmit and receive data buffers since multiple data bytes can be associated with a single command byte, the tws is designed with transmit and receive buffers to prevent data loss and reduce cpu overhead during a communication sequence. data received from the master is directed to an 8 byte deep receive first in, first out buffer (rxd fifo) until read by the cpu. data to be transmitted by the ds2790 is stored in a separate 8-byte transmit fifo buffer (txd fifo) until the master reads it. if the rxd fifo buffer becomes completely full or the txd fifo buffer becomes completely empty during communication, the interface will begin clock extending the bus to maintain data integrity. the cpu has access to the txd and rxd fifos through the transmit/receive data register (twstxd/rxd). during a master read (tws transmit) data is pushed onto the txd fifo by writing to the twstxd/rxd register. likewise, during a master write (tws receive), the cpu can pull data off the rxd fifo by reading the twstxd/rxd register.
ds2790 programmable 1-cell li-ion fuel gauge and protector 28 of 41 both the txd and rxd fifos are flushed when a new command byte is accepted (command handshaking is enabled and the twscmd register is not busy, or when command handshaking is disabled). in the tws fifo register (twsfif), lrx[3:0] reports the number of received bytes waiting in the rxd fifo and ltx[3:0] reports the number of bytes in the txd fifo to be transmitted. timeouts and clock extending clock extending during a ds2790 receive event (master write), is applied to delay the rising edge of scl just before the ack symbols after the command byte is sent, and to any ack symbols thereafter. if the rxd fifo is full, the clock low time just prior to the ack symbol will be extended until a timeout occurs or the rxd fifo has been read and is no longer full. clock extending during a ds2790 transmit event (master read), is applied to delay the rising edge of scl just after the ack symbol following the address, and to any ack symbols thereafter. if the txd fifo is empty, the clock low time just after the ack symbol will be extended until a timeout occurs of the txd fifo has been written and is no longer empty. the t timeout and t low:sext timers analyze the 2-wire bus for timeout conditions, and can cause the tws to reset its internal state machine. these timers allow the bus to remain available even after bus fault conditions such as device hot swapping. without the timers, such scenarios could result in a bus lock-up preventing all further communication. the t timeout timer begins counting on the falling edge of clock, and is reset on the rising edge of clock. if the timer ever reaches the t timeout value (nominal 30ms), the clock line is released, after a short delay the data line is also released. the t low:sext timer is reset whenever a start condition occurs on the bus. specifically note that the timer is not reset during a repeated start condition. the timer counts while the tws is holding the clock low. the timer does not count when a master or other slave device is holding the clock low. the timer is stopped on a stop condition. if the timer times out (nominal 15ms), the clock line is released, followed by the data line. the t timeout timer can be disabled using the tto_dis bit in the twscfg register, while t low:sext can be disabled using the tls_dis bit. the tout_long bit in the twscfg register allows the nominal value of the timeout conditions to be increased by a factor of four. command codes the ds2790 has two reserved command codes: a software power on reset (por) of the ic, and an instruction to begin program loading over the 2-wire interface. each command code is first enabled by transmitting the command enable (feh) followed directly by the command instruction. there are no associated data bytes with either command. any 2-wire communication between the two instructions negates the operation. see the maxq family user's guide: ds2790 supplement for the 2-wire programming procedure. these command codes are fixed inside the ds2970 and cannot be altered. system firmware should avoid using feh as a command code during during device operation. table 11. 2-wire interface command codes command hex code purpose command enable feh enable soft por or program command. soft por repeated feh causes a reset of the part. request programming fdh initiates programming over 2-wire interface. available 00h-fch, ffh defined by application firmware.
ds2790 programmable 1-cell li-ion fuel gauge and protector 29 of 41 figure 10. 2-wire communication examples s slave address wr ack master to slave slave to master command byte ack data byte 1 ack p s slave address wr ack command byte ack ack data byte 1 ack p s rd data byte 2 nack data byte 8 ack data byte 9 ack ... potential clock extension if cmd release latch clear, cmd_hm_dis = 0, and cmd_hm = 0 potential clock extension if cmd release latch clear, cmd_hm_dis = 0, and cmd_hm = 0 potential clock extension when rxd is full. potential clock extension when txd is empty. i 2 c/smbus write data sequence i 2 c/smbus read data sequence slave address data byte n ack ... data byte 1 ack s slave address wr ack feh ack p ds2790 software por sequence s slave address wr ack feh ack p command enable repeated feh generates software por s slave address wr ack feh ack p ds2790 2-wire programming request s slave address wr ack fdh ack p command enable initiate programming over the 2-wire interface 2-wire programming sequence begins ...
ds2790 programmable 1-cell li-ion fuel gauge and protector 30 of 41 analog-to-digital conversion the ds2790 performs real-time measurements of system temperature, voltage, current, and accumulated current. the ds2790?s analog-to-digital converter is controlled by an internal state machine that sequences the measurements, and stores the results in memory. the conversion results of the adc are mapped into data memory starting at word address 6003h, as shown in table 12. programs should read a measurement value as a word to ensure that the value does not change between instructions. the ds2790 current measurement system is designed to provide timely data on charge and discharge current at a moderate resolution level while simultaneously accumulating high resolution average data to support accurate coulomb counting. current is measured by sampling the voltage drop across a series sense resistor, r sns , connected between sns1 and sns2. individual current samples are taken every 1/f samp (687s). all samples are averaged to report current, average current, and accumulated current values. the ds2790 measures voltage as a difference between the v in pin and analog ground pin avss. individual voltage samples are taken approximately every 1/f samp (687s). multiple samples are averaged to update the average voltage register. the ds2790 measures temperature directly on chip. individual temperature samples are taken every 10/f samp (6.87ms). multiple samples are averaged to update the average temperature register. table 22. adc related registers word address access description 6003h read only voltage register 6004h read only current register 6005h read only temperature register 6006h r/w accumulated current register 6007h read only accumulated current (middle word) 6008h read only accumulated current (lower word) 6009h read only average current register 600ah r/w adc configuration register current measurement the voltage signal developed across the sense resistor (between sns1 and sns2) is differentially sampled by the adc inputs via internal 10k ? resistors connected between sns1 and is1, and sns2 and is2. isolating the adc inputs (is1 and is2 pins) from the sense resistor with 10k ? facilitates the use of an rc filter by adding a single external capacitor. the rc filter extends the effective input range beyond 64mv in pulse-load or pulse-charge applications. the adc accurately measures large peak signals as long as the differential signal level at is1 and is2 does not exceed 64mv. the current register reports the average of 128 individual current samples every 88ms. the reported value represents the average current during the 88ms measurement period. the average current register reports the average of 4096 current samples and is updated every 2.8s. figures 11 and 12 specify the update interval and units for the current and average current registers. values are posted in two?s compliment format. positive values represent charge currents (v is1 > v is2 ) and negative values represent discharge currents (v is2 > v is1 ). positive currents above the maximum register value are reported at the maximum value, 7fffh. negative currents below the minimum register value are reported at the minimum value, 8000h.
ds2790 programmable 1-cell li-ion fuel gauge and protector 31 of 41 figure 11. current register format 12-bit + sign resolution (13-bit), 88ms update interval word address 6004h s 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 x x x msb lsb ?s?: sign bit(s) units: 2 0 = 15.625 v/rsns figure 12. average current register format 15-bit + sign resolution (16-bit), 2.8s update interval word address 6009h s 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb ?s?: sign bit(s) units: 2 0 = 1.953 v/rsns current offset correction continuous offset cancellation is performed automatically to correct for offsets in the current measurement system. individual values reported by the current register have a maximum offset of 0.5 bits (7.8125v). individual values reported in the average current register have a maximum offset of 4 bits (7.8125v). current accumulation the ds2790 measures current for coulomb-counting purposes, with an accuracy of 2% 3.9v over a range of 64mv. using a 15m ? sense resistor, current accumulation is performed over a range of 4.26a while measuring standby currents with an accuracy of 195a. current measurements are internally summed, or accumulated, with the results displayed in the accumulated current register (acr). the accuracy of the acr is dependent on both the current measurement and the accumulation timebase. the 16-bit acr has a range of 204.8mvh with a resolution of 6.25vh. accumulation of charge current above the maximum register value is reported at the maximum value; conversely, accumulation of discharge current below the minimum register value is reported at the minimum value. read and write access is allowed to the acr. figure 13. accumulated current register format word address 6006h s 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb ?s?: sign bit(s) units: 2 0 = 6.25 vh/rsns the lower 32 bits of acr resolution ( bits 2 -1 to 2 -32 ) can be read by firmware from address locations 6007h and 6008h respectively. note that since the lower bits are from separate address words it cannot be guaranteed that they will contain data from the same measurement as the main acr register at the time of reading. however, two consecutive reads from addresses 6006h?6008h that contain the same data esures that all data is from the same measurement. when the acr register is written, the lower acr bits are automatically cleared.
ds2790 programmable 1-cell li-ion fuel gauge and protector 32 of 41 accumulation blanking in order to avoid the accumulation of small positive offset errors over long periods, an offset blanking filter is provided. the blanking filter is enabled by setting the oben bit in the adc configuration register. when oben is set, charge currents (positive values from the current register) less than 62.5 v are not accumulated in the acr. the minimum charge current accumulated in the acr is 4.167ma for rsns = 0.015 . accumulation bias systematic errors or an application preference can require the application of an arbitrary bias to the current accumulation process. the accumulation bias value sets a user programmed positive or negative bias to the current accumulation process. the accumulation bias value can be used to estimate battery currents that do not flow through the sense resistor, estimate battery self-discharge, or correct for offset error accumulated in the acr register. the user programmed two?s compliment value is added to the acr once per current sample. the bias control is applied in 0.98 v increments over a 125 v range. when using a 15m sense resistor, the bias control can be adjusted in 65.3 a increments over a 8.33ma range. the accumulation bias bit field is located in the upper byte of the adc configuration register. figure 14. accumulation bias field upper byte of word address 600ah s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb ?s?: sign bit units: 2 0 = 0.98 v/rsns voltage measurement the ds2790 continually measures the voltage between pins v in and av ss over a 0.0v to v fs range, and the voltage register is updated in two?s-complement format every 3.4ms with a resolution of 4.88mv. voltages above the maximum register value are reported as the maximum value. figure 15. voltage register format word address 6003h s 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 x x x x x msb lsb ?s?: sign bit units: 2 0 = 4.88 mv temperature measurement the ds2790 uses an integrated temperature sensor to continually measure battery temperature. temperature measurements are updated in the temperature register every 220ms in two?s-complement format with a resolution of 0.125c over a 127c range. the temperature register format is shown in figure 16.
ds2790 programmable 1-cell li-ion fuel gauge and protector 33 of 41 figure 16. temperature register format word address 6005h s 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 x x x x x msb lsb ?s?: sign bit units: 2 0 = 0.125 c adc configuration register the adc configuration register located at word address 600ah controls current measurement bias and offset blanking as well as current fault limits for the protector circuitry. adc configuration register bits are read and write accessable by application code. coct, doct, and scdt bit functionality is described under lithium-ion protection. figure 17. adc configuration register format address 600ah bit definition field bit format allowable values ibias 15:8 r/w accumulation register bias 8-bit 2?s complement value that is added to the acr on every update. coct 7:6 r/w charge overcurrent threshold
see lithium-ion protection. see v oc in the specification table for limit tolerances. 0 0 = 16mv v oc 0 1 = 32mv v oc 1 0 = 48mv v oc 1 1 = 64mv v oc doct 5:4 r/w discharge overcurrent and short circuit thresholds
see lithium-ion protection. see v oc and v sc in the specification table for limit tolerances. 0 0 = 16mv v oc , 100mv v sc 0 1 = 32mv v oc , 140mv v sc 1 0 = 48mv v oc , 180mv v sc 1 1 = 64mv v oc , 220mv v sc scdt 3 r/w short circuit delay time
see lithium-ion protection. see t scd in the specification table for limit tolerances. 0 = 250s 1 = 2.0ms reserved 2:1 read only undefined oben 0 r/w offset blanking enable 0 = all current measurements accumulated into the acr. 1 = positive current measurements less than 62.5v/r sns not accumulated into the acr.
ds2790 programmable 1-cell li-ion fuel gauge and protector 34 of 41 lithium-ion protection for safety, lithium-ion cell protection functions are handled by a completely independent state machine. application firmware can disable the protection fets, but is not able to override the protector and enable the fets. during active operation (cpu or analog mode), the ds2790 constantly monitors cell voltage and current to protect the battery from overcharge (overvoltage), overdischarge (undervoltage), excessive charge and discharge currents (overcurrent, short circuit), and extreme temperatures (overtemperature, undertemperature). protection conditions and ds2790 responses are described in the following sections and summarized in table 13 and figure 18. table 13. lithium-ion protection conditions and ds2790 responses activation condition threshold delay response release threshold overvoltage v in > v ov t ovd cc low v in < v ce , or v is -2mv undervoltage v in < v uv t uvd cc low, dc low v pls > v in + 0.15v (1) (charger connected) overcurrent, charge v is > v oc t ocd cc low, dc low v pls < v dd - v tp (2) overcurrent, discharge v is < -v oc t ocd dc low v pls > v dd - v tp (3) short circuit v is > v sc t scd dc low v pls > v dd - v tp (3) charge overtemperature t a > t ch (4) cc low t a t ch (4) charge undertemperature t a t cl (4) cc low t a > t cl (4) discharge overtemperature t a > t dh (4) dc low t a t dh (4) discharge undertemperature t a t dl (4) dc low t a > t dl (4) v is = v is1 - v is2 . off = v pls for cc and v dd for dc. . all voltages are with respect to v ss . i sns references current delivered from pin sns. under-/overtemp conditions have no activation delay from the time the temperature register updates. the temperature register r esult is an average over 220ms, this provides protection against the mosfets oscillating. note 1: if v in < v uv , release is delayed until the recovery charge current (i rc ) charges the battery and allows v in to exceed v uv . note 2: with test current i tst flowing from pls to v ss (pulldown on pls). note 3: with test current i tst flowing from v dd to pls (pullup on pls). note 4: temperature faults must be enabled through the tlime bit in password protected trim memory. temperature fault thresholds are determined by the state of tlim[1:0]. see password protected user trim. overvoltage, ov. if the cell voltage on v in exceeds the overvoltage threshold, v ov , for a period longer than overvoltage delay, t ovd , the ds2790 shuts off the external charge fet and sets the ovf bit in the protection register. when the cell voltage falls below charge enable threshold v ce , the ds2790 re-enables the charge fet (unless another protection condition prevents it). discharging remains enabled during overvoltage, and the ds2790 re-enables the charge fet before v in < v ce if a discharge current of v is -2mv is detected. undervoltage, uv. if the voltage of the cell drops below undervoltage threshold, v uv , for a period longer than undervoltage delay, t uvd , the ds2790 shuts off the charge and discharge fets and sets the uvf bit in the protection register. the ds2790 provides a current-limited (i rc ) recovery charge path from pls to v dd to gently charge severely depleted cells. the recovery path is enabled when 0 v in < v ce . once v in exceeds v uv the ds2790 returns to normal operation. charge overcurrent, coc. the voltage difference between the is1 pin and the is2 pin (v is = v is1 - v is2 ) is the filtered voltage drop across the current-sense resistor. if v is exceeds overcurrent threshold v oc for a period longer than overcurrent delay t ocd , the ds2790 shuts off both external fets and sets the cocf bit in the protection register. the charge current path is not re-established until the voltage on the pls pin drops below v dd - v tp . the ds2790 provides a test current of value i tst from pls to v ss to pull pls down to detect the removal of the offending charge current source. the charge v oc limit is programmable through the coct bits in the adc configuration register.
ds2790 programmable 1-cell li-ion fuel gauge and protector 35 of 41 discharge overcurrent, doc. if v is is less than -v oc for a period longer than t ocd , the ds2790 shuts off the external discharge fet and sets the docf bit in the protection register. the discharge current path is not re- established until the voltage on pls rises above v dd - v tp . the ds2790 provides a test current of value i tst from v dd to pls to pull pls up to detect the removal of the offending low-impedance load. the discharge v oc limit is programmable through the doct bits of the adc configuration register. short circuit, sc. if the voltage on the sns2 pin with respect to sns1 exceeds short-circuit threshold v sc1 for a period longer than short-circuit delay t scd , the ds2790 shuts off the external discharge fet and sets the scf bit in the protection register. the discharge current path is not re-established until the voltage on pls rises above v dd - v tp . the ds2790 provides a test current of value i tst from v dd to pls to pull pls up to detect the removal of the short circuit. the v sc limit is programmable through the doct bits of the adc configuration register. the t scd limit is programmable through the scdt bit of the adc configuration register. if a short circuit event collapses v dd , a secondary short circuit protection function disables the discharge fet within a period of t sscd. charge/discharge over-/undertemperature, dot, dut. assuming no other fault conditions, the cc pin is enabled when the temperature is greather than t ch , or less than or equal to t cl . the dc pin is disabled when the temperature is greater than t dh , or less than or equal to t dl . when the temperature is inside these ranges, both control pins are enable. there is no hysteresis or delay period associated with temperature protection. temperature protection must be enabled by user code by setting the tlime bit. over-/undertemperature limits are defined by tlim0 and tlim1 bits located in password protected memory. figure 18. lithium-ion protection circuitry example waveforms summary. all of the protection conditions described above are and?ed together with temperature protection functions to affect the cc and dc outputs. dc = ( undervoltage ) and ( overcurrent , either direction) and ( short circuit ) and ( discharge overtemperature if enabled) and ( discharge undertemperature if enabled) and (de = 1) and sleep cc = ( overvoltage ) and ( undervoltage ) and ( overcurrent , charge direction) and ( charge overtemperature if enabled) and ( charge undertemperature if enabled) and (ce = 1) and sleep uvf v ov v ce v uv v cell v is charge discharge cc dc -v sc v oc -v oc 0 t scd t ocd t ocd t uvd t ovd v cp v cp v dd v pls t ovd (note 1) note 1: to allow the device to react quickly to short circuits, detection occurs on the sns pin rather than on the filtered is1 and is2 pins. the actual short-circuit detect condition is v sns2 - v sns1 > v sc1 .
ds2790 programmable 1-cell li-ion fuel gauge and protector 36 of 41 protection register the protection register allows system software to determine if a protection fault condition has occurred and what triggered the protection fault. when a protection fault occurs, its corresponding protection flag is set. the flag will remain set until system software clears the bit after the fault is no longer present. system software can also disable charging or discharging by clearing the charge enable or discharge enable bits, or system software can completely disable the adc and/or the protection fets using the pmm bits. there is no way for system software to override a fault condition and enable the fets. figure 19. protection register format (prot) field bit format definition cocf 15 r/w charge overcurrent flag. set to 1 by an coc fault condition. can only be reset by system software after fault is corrected. docf 14 r/w discharge overcurrent flag. set to 1 by a doc fault condition. can only be reset by system software after fault is corrected. scf 13 r/w short circuit flag. set to 1 by a sc fault condition. can only be reset by system software after fault is corrected. ovf 12 r/w overvoltage flag. set to 1 by an ov fault condition. can only be reset by system software after fault is corrected. uvf 11 r/w undervoltage flag. set to 1 by a uv fault condition. can only be reset by system software after fault is corrected. reserved 10 read only undefined cc 9 read only cc pin mirror. this bit mirrors the state of the cc pin. dc 8 read only dc pin mirror. this bit mirrors the state of the dc pin. reserved 7:4 read only undefined ce 3 r/w charge enable. 0 = charge fet is disabled. 1 = charge fet is enabled unless disabled by fault. writing this bit to 1 will not override a fault condition. de 2 r/w discharge enable. 0 = discharge fet is disabled. 1 = discharge fet is enabled unless disabled by fault. writing this bit to 1 will not override a fault condition. pmm 1:0 r/w protection and measurement modes. 0 0 = adc disabled, cc and dc low. 0 1 = adc enabled, cc and dc low. 1 0 = adc enabled, cc and dc low. 1 1 = adc enabled, cc and dc high. adjusting protection thresholds the protection thresholds are set in two locations. the charge overcurrent threshold, discharge overcurrent threshold, short-circuit current threshold, and short-circuit delay thresholds are set in the adc configuration register location 600ah. values for overvoltage, undervoltage, and all temperature thresholds are stored in the password protected memory. see the password protected user trim section. high side n-channe l protection fets the ds2790 controls charging and discharging through external high-side n-fets controlled through the cc and dc pins. an internal charge pump generates the voltage needed to drive the external fets. an external capacitor connected between the cp and vss pins stores the charge needed for the ds2790 to maintain the cc and dc outputs. to disable discharging, the ds2790 internally connects dc to v ss . to disable charging, the ds2790 internally connects cc to v dd . to enable charging or discharging, the ds2790 drives the appropriate fet gate to v ocp by internally pulling cc and dc up to the cp voltage. the system designer should consider the following when selecting external fets:
ds2790 programmable 1-cell li-ion fuel gauge and protector 37 of 41 gate to source voltage. the external fets must be able to withstand a voltage between their gate and source pins of at least the charge pump voltage v ocp to prevent damage. gate leakage. the gate leakage of both external fets must be smaller than 0.9a to ensure cc and dc meet the v ocp specification. password protected user trim system software has the ability to change temperature and voltage protection levels, 2-wire slave address, and current measurement gain of the ic through the user trim in program eeprom (word addresses 001dh?001fh). the user trim values are enabled through the trim key in the lower byte of address 001dh. if the trim key is set to 76h, the user trim values replace the default trim values, if the trim key is set to any other value, default trim is selected. note that either all user trim values are enabled or none are enabled. figure 20. shows the format of all values that can be adjusted and their default trim values. figure 20. user trim registers address 001dh bit definition field bit format allowable values unused 15 r/w undefined
general purpose slave address 14:8 r/w 2-wire slave address valid only if trim key = 76h default = 0001011b trim key 7:0 r/w trim key enables or disables all other user trim values. 76h = all user trim values valid. other = all user trim values invalid. default trim used. address 001eh bit definition field bit format allowable values ig 15:8 r/w current gain trim these bits adjust the current gain by +/-25%. the most significant bit is the 2?s compliment sign bit, 1lsb = 0.195%. example: a4h (-92d) adjusts the trim by -17.94%. valid only if trim key = 76h default = factory trim value srtc 7:0 r/w sense resistor temperature coefficient these bits adjust the current gain based on temperature of the sense resistor. 1lsb = 30.5ppm/oc. example: 1ah (26d) adjusts current measurements for a sense resistor with a 793ppm/oc temperature coefficient. valid only if trim key = 76h default = 00h
ds2790 programmable 1-cell li-ion fuel gauge and protector 38 of 41 address 001fh bit definition field bit format allowable values unused 15:13 r/w undefined ? general purpose uvt 12:8 r/w undervoltage threshold the undervoltage threshold ranges from 2.30v to 2.90v and is calculated by the equation: v uv = 2.90v ? 0.0195v uvt[4:0] valid only if trim key = 76h default = 17h (2.45v) tlime 7 r/w temperature limit enable 0 = disables lithium-ion protection based on temperature. 1 = enables temperature protection defined by tlim[1:0] bits. valid only if trim key = 76h default = 0 tlim 6:5 r/w temperature limit thresholds t cl t ch t dl t dh 0 0 = -3oc 53oc -23oc 63oc 0 1 = -3oc 58oc -23oc 68oc 1 0 = -23oc 73oc -23oc 73oc 1 1 = -43oc 88oc -43oc 88oc valid only if trim key = 76h and tlime = 1 default = 0 0 ovt 4:0 r/w overvoltage threshold the overvoltage threshold ranges from 4.25v to 4.55v and is calculated by the equation: v ov = 4.25v + 0.00977v ovt[4:0] the enable threshold v ce is always fixed at 0.1v below v ov . valid only if trim key = 76h default = 0ah (4.35v)
ds2790 programmable 1-cell li-ion fuel gauge and protector 39 of 41 in-circuit debug embedded debugging capability is available through the jtag-compatible test access port. embedded debug hardware and embedded rom firmware provide in-circuit debugging capability to the user application, eliminating the need for an expensive in-circuit emulator. figure 21 shows a block diagram of the in-circuit debugger. the in- circuit debug features include: a hardware debug engine, a set of registers able to set breakpoints on register, code, or data accesses (icda, icdb, icdc, icdd, icdf, icdt0, and icdt1) a set of debug service routines stored in the utility rom. figure 21. in-circuit debugger tms tck tdi tdo tap controller debug engine utility rom debug service routines cpu control breakpoint address data the embedded hardware debug engine is an independent hardware block in the microcontroller. the debug engine can monitor internal activities and interact with selected internal registers while the cpu is executing user code. collectively, the hardware and software features allow two basic modes of in-circuit debugging: background mode allows the host to configure and set up the in-circuit debugger while the cpu continues to execute the application software at full speed. debug mode can be invoked from background mode. debug mode allows the debug engine to take control of the cpu, providing read/write access to internal registers and memory, and single step trace operation.
ds2790 programmable 1-cell li-ion fuel gauge and protector 40 of 41 applications the low-power, high-performance risc architecture of the ds2790 makes it an excellent fit for many portable or battery-powered applications that require cost-effective computing and analog measurement capability. the high- throughput core is programmable in-circuit over the 2-wire and jtag interfaces, allowing for firmware upgrades, and ease of code development. applications benefit from a wide range of peripheral interfaces, allowing the microcontroller to communicate with many external devices. with an integrated charge pump, high side n-fet drivers, and adc?s capable of measuring cell voltage, and monitoring current. the ds2790?s high level of integration reduces component count and board space, critical factors in the design of portable systems. the ds2790 is ideally suited for applications such as fuel gauging, sensor conditioning, and data collection. additional documentation designers must have four documents to fully use all the features of this device. this data sheet contains pin descriptions, feature overviews, and electrical specifications. errata sheets contain deviations from published specifications. the user?s guides offer detailed information about device features and operation. the following documents can be downloaded from www.maxim-ic.com/ds2790 . the ds2790 data sheet, which contains electrical/timing specifications and pin descriptions, available at www.maxim-ic.com/ds2790 . the ds2790 errata sheet, available at www.maxim-ic.com/errata . the maxq family user's guide , which contains detailed information on core features and operation, including programming. the maxq family user's guide: ds2790 supplement , which contains detailed information on features specific to the ds2790. development and technical support a variety of highly versatile, affordably priced development tools for this microcontroller are available from maxim/dallas semiconductor and third-party suppliers, including: compilers in-circuit emulators integrated development environments (ides) serial-to-jtag converters for programming and debugging usb-to-jtag converters for programming and debugging technical support is available through email at batterymanagement.support@dalsemi.com
ds2790 programmable 1-cell li-ion fuel gauge and protector 41 of 41 pin configuration 1 3 2 4 cp nc nc pls 8mm 4mm tdfn-28 5 7 6 8 9 11 10 12 13 14 scl cc dc sda sns2 tms/int1/p0.1 tdi/int0/p0.0 is2 nc nc DS2790G+ 28 26 27 25 vin nc nc vdd 24 22 23 21 20 18 19 17 16 15 p0.3/tclk p0.4/tdo p0.5 p0.2/rst sns1 avss vss is1 nc nc 1 3 2 4 cp nc nc pls tssop 28 5 7 6 8 9 11 10 12 13 14 scl cc dc sda sns2 tms/int1/p0.1 tdi/int0/p0.0 is2 nc nc ds2790e+ 28 26 27 25 vin nc nc vdd 24 22 23 21 20 18 19 17 16 15 p0.3/tclk p0.4/tdo p0.5 p0.2/rst sns1 avss vss is1 nc nc pad package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/dallaspackinfo .) purchase of i 2 c components from maxim integrated products, inc., or one of its sublicensed associate companies, conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification defined by philips.

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